Operation of a plurality of visual display units from one screen controller

ABSTRACT

Method and circuit arrangement for independent operation of a plurality of visual display units ( 210-216 ) from one screen control unit ( 10 ), which can emit clock signals and a number of character-related or pixel-related video data signals corresponding to the line and column resolution of a two-dimensional rectangular raster image which is to be displayed on a visual display unit. Rectangular subareas of a full screen format are in this case displayed on one of the visual display units ( 210-216 ).

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method and a circuit arrangement forindependent operation of a plurality of visual display units from onescreen control unit.

2. Description of the Related Art

In equipment whose control system is based on PC (person computer)technology, a visual display unit is in general operated from a monitorinterface which operates, for example, on the VGA Standard and isprovided by a special screen control unit which in the example is aso-called VGA controller. The PC software operating system includes anappropriate driver program. If the intention is to connect a pluralityof visual display units which are intended to indicate differentinformation at the same time, a dedicated screen control unit isrequired for each visual display unit.

A plurality of visual display units are in general required wherever anumber of people are monitoring data acquisition or processing processesor where different people are each intended to have access to only apart of the overall information. This is the situation, for example,with cash registers or with service terminals which are equipped atleast with an operator display and a customer display. In addition, ananimation screen is frequently provided for displaying advertising orgeneral information, or else a numerical display device for displayingthe reservation number of a next customers To provide a screen controlunit for each display unit consumes space and is expensive, as well ashaving a disadvantageous effect on the processing speed of the PC.

In U.S. Pat. No. 4 965 559, it has therefore been proposed for aplurality of visual display units to be operated from one screen controlunit, which emits clock signals and a number of character-related orpixel-related video data signals corresponding to the line and columnresolution of a two-dimensional rectangular raster image. In this case,the clock and video data signals which belong to rectangular subareas ofthe raster image are in each case supplied to a visual display unit.However, in addition, an individual assignment or matching device(look-up table) is required for each visual display unit.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a method and a circuitarrangement which allow the independent operation of a plurality ofvisual display units from one screen control unit.

The invention provides a method.

The invention uses a screen control unit which can emit clock signalsand a number of character-related or pixel-related video data signalscorresponding to the line and column resolution of a two-dimensionalrectangular raster image which is to be displayed on a visual displayunit. One such control unit is, for example, a VGA controller which isknown from the PC (person computer) world and whose resolution can bechanged between different formats. One frequently used format has aresolution of 640 pixels horizontally and 480 pixels vertically in thegraphics mode, and 80 characters/line and 30 lines in the charactermode, one character being allocated an area of 8×16 pixels. The formatis related to a so-called full screen, as is known from CRT visualdisplay units. The individual pixels and the characters are representedby video data signals. In order to simplify the presentation of theinvention, the following description is always based on a full format of640×480 pixels, corresponding to 30×80 characters. However, theinvention can also be applied to any other format.

In addition to full screens, visual display units are also known whichhave a reduced picture field, for example 320×240, 240×64 or 120×64pixels, corresponding to 15 lines×40 characters, 4×30 or 4×x15characters. If the video data signals and the clock signals whichtransfer them for rectangular sub-areas in the raster frame are suppliedto in each case one visual display unit, then a plurality of visualdisplay units can be operated from a single screen control unit.

These visual display units can be arranged physically and separatelyfrom one another, for example one on the cashier's side and a second onthe customer's side of a cash register, a third in a so-called tillindicator above a till workstation, and a fourth anywhere on the salesfloor of a large shop.

If it is intended to operate the individual visual display unitsentirely independently of one another in terms of the information to bedisplayed, the sum of the characters and pixels which can be displayedon all the visual display units must be less than or equal to the numberof data signals emitted by the screen control unit.

However, it is also frequently desirable to display at least parts ofthe information on a number of visual display units. For example, ascreen line which includes the date and time could be displayed on thecustomer's display and the operator's display. To do this, the videodata and clock signals which represent this screen line must be suppliedto both visual display units. In this case, the sum of the charactersand pixels which are to be displayed on all the visual display units maybe greater than the number of data signals emitted by the screen controlunit.

Further features and advantages of the invention result from thefollowing description, which explains the invention with reference to aplurality of exemplary embodiments and in conjunction with the attacheddrawings, in which:

FIG. 1 is a block diagram which shows a circuit arrangement having twovisual display units,

FIG. 2 is a block diagram which shows a circuit arrangement having fourvisual display units, and

FIG. 3 is a block diagram which shows a circuit arrangement having adual scan visual display unit according to the prior art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 3 shows a block diagram of a known circuit arrangement having afull LCD screen 310 with 640×480 pixels (corresponding to 30×80characters), which is designed using DSTN (Dual Scan Super TwistedNematic) technology. As is characteristic of dual scan LCD visualdisplay units, the visual display unit 310 is split into an upper region312 and a lower region 314. The upper region 312 is connected to avisual display unit control unit 10 via an upper data bus UDB, and thelower region 314 is connected to a visual display unit control unit 10via a lower data bus LDB—the visual display unit control unit 10 being aso-called VGA controller. As a further connection between the visualdisplay unit 310 and the VGA controller 10, a control bus CB is providedwhich is allocated to both screen regions 312 and 314 and on which theclock and control signals are carried which are necessary for dual scanLCD visual display units and are known per se. For its part, the VGAcontroller 10 is driven via a further bus 14, from the arithmetic unit12 of a PC, which is otherwise not illustrated. The essential part of aVGA controller of this said type is, for example, the component No.65535 “Flat Panel/CRT VGA Controller”, from the company Chips andTechnologies, Inc., to which only a VGA BIOS and a video replay memorynow need be connected.

The present invention makes use of the characteristics of a “FlatPanel/CRT VGA Controller” of this said type. In this case, parts whichoccur more than once are given the same reference characters in thefollowing text.

FIG. 1 shows a block diagram of the connection of two LCD visual displayunits 110 and 112, which operate using a single scan method that isknown per se, to a VGA controller 10 which is set up for the dual scanmode. The data input D of one visual display unit 110 is connected viathe upper data bus UDB to the VGA controller 10, and the data input D ofthe other visual display unit 112 is connected via the lower data busLDB to the VGA controller 10. The control bus CB is connected inparallel to the clock signal input C of the two visual display units 110and 112. The connection of the VGA controller 10 to an arithmetic unit12 via a bus 14 is made in a corresponding manner to the prior artillustrated in FIG. 3.

In the case of mutually independent operation, the visual display units110 and 112 may have a maximum format of 320×480 pixels, correspondingto 15×x80 characters. In the text mode, the first fifteen lines of aframe are displayed on the visual display unit 110 which is connected tothe upper data bus UDB, and the second fifteen lines of a frame aredisplayed on the visual display unit 112 which is connected to the lowerdata bus LDB. A corresponding situation applies to the graphics mode.However, commercially available smaller formats with, for example,320×240 pixels, corresponding to 15 lines of 40 characters each, canalso be connected, although they then only partially utilize the displaycapacity of the full format.

FIG. 2 shows a block diagram of the connection of four LCD visualdisplay units 210, 212, 214 and 216, which are operated using the singlescan method, to a VGA controller 10 which is set up for the dual scanmode. The data inputs D of the visual display units 210 and 212 areconnected via the upper data bus UDB to the VGA controller 10, and thedata inputs D of the visual display units 214 and 216 are connected viathe lower data bus LDB to the VGA controller 10. The clock signal inputsC of the visual display units 210 and 214 are connected directly to thecontrol bus CB, while the clock signal inputs C of the visual displayunits 212 and 216 are connected to a control bus CB′, upstream of whicha gate circuit 218 having a counter is connected. This gate circuit 218suppresses the clock signals for video information items which aredisplayed on the directly driven visual display units 210 and 214.

In the case of mutually independent operation, the visual display units210-216 may have a maximum format of 320×240 pixels, corresponding to15×40 characters. In the text mode, positions 1-40 of lines 1-15 of aframe are displayed on the first visual display unit 210, positions41-80 of lines 1-15 are displayed on the visual display unit 212,positions 1-40 of lines 16-30 are displayed on visual display unit 214,and positions 41-80 of lines 16-30 are displayed on visual display unit216. The visual display unit 210 thus forms the left-hand upper quarterof a frame, the visual display unit 212 forms the right-hand upperquarter, the visual display unit 214 forms the left-hand lower quarter,and the screen 216 forms the right-hand lower quarter. A correspondingsituation applies to the graphics mode. Visual display units with asmaller format may also be connected. The display capacity of the fullformat is then only partially utilized.

If the left-hand visual display units 210 and 214 have a differentnumber of character positions, a dedicated gate circuit must be assignedto each right-hand visual display unit, or a gate circuit having aplurality of outputs is used, which emit clock signals after therespectively required number of steps.

The VGA controller 10 is once again connected via a bus 14 to anarithmetic unit 12 in a corresponding manner to the prior artillustrated in FIG. 3.

The exemplary embodiments which have been explained with reference toFIGS. 1 and 2 can also be combined with one another, for example, avisual display unit having 15×80 characters, corresponding to 320×480pixels, can be connected to the upper data bus UDB, and two visualdisplay units having 15×40 characters, corresponding to 320×240 pixelseach, can be connected to the lower data bus LDB. In the text mode,positions 1-80 of lines 1-15 of a frame are then displayed on the uppervisual display unit, and positions 1-40 or 41-80 of lines 16-30 aredisplayed on the lower visual display units.

In all the examples, the visual display units may also have a largerformat. The information intended for one screen then occupies only aportion of the screen area, while information which is also displayed onan adjacent visual display unit appears on the remaining area. This canbe utilized in a simple manner for simultaneously displaying informationon a number of visual display units. If this is not desired, it isnecessary to suppress the relaying of the video data and clock signalsrelating to the last-mentioned information items.

The operation of a number of visual display units in the indicatedmanner from a single screen control unit 10 has the advantage that,instead of these visual display units, a single full screen may also beconnected without the display programs having to be changed. When userprograms are being created and tested, the contents of the visualdisplay units 110, 112 and 210-216 are displayed to the programmer assubareas on a single visual display unit. It is also possible to createand to test such programs on a PC with standard equipment, without thevarious visual display units having to be available. Similar advantagesalso result during the installation and maintenance of an installationwhose visual display units under some circumstances are spread over alarge area and therefore cannot be seen at a glance.

Although other modifications and changes may be suggested by thoseskilled in the art, it is the intention of the inventor to embody withinthe patent warranted hereon all changes and modifications as reasonablyand properly come within the scope of their contribution to the art.

What is claimed is:
 1. A method for independent operation of a pluralityof visual display units from one screen control unit, comprising thesteps of: emitting clock signals and a number of character-related orpixel-related video data signals corresponding to line and columnresolution of a two-dimensional rectangular raster image which is to bedisplayed on a full screen, supplying the clock and video data signalsassociated with rectangular subareas of the two-dimensional rectangularraster image to each visual display unit, and a sum of character areasor pixels which can be driven separately on all the visual display unitsbeing less than or equal to a number of clock and video data signalswhich are emitted by the screen control unit operating the visualdisplay units in the single scan mode from a screen control unit whichis set to dual scan mode. 2.The method as claimed in claim 1, wherein asum of the characters and pixels which can be displayed on all thevisual display units is greater than a number of video data signalswhich are emitted by the screen control unit, and further comprising:supplying at least one of clock and video data signals to at least apart of a subarea of more than one visual display unit.
 3. A circuitarrangement for for independent operation of two visual display unitswhich are operated in the single scan mode, and which each have a datainput and a clock signal input and one of which is intended fordisplaying an upper subarea of a frame, and the other of which isintended for displaying a lower subarea of a frame, comprising: screencontrol unit which is set up for dual scan mode and has an upper databus and a lower data bus and a control bus, and the clock signal inputsof both of said visual display units being connected in parallel to thecontrol bus of the screen control unit, the data input of one of saidtwo visual display units being connected to the upper data bus, and thedata input of an other of said two visual display units being connectedto the lower data bus of the screen control unit. 4.A circuitarrangement for independent operation of two visual display units whichare operated in the single scan mode and have a data input and a clocksignal input, and one of which is intended for displaying a left-handsubarea of a frame and an other of which is intended for displaying aright-hand subarea of a frame, comprising: screen control unit which isset up for dual scan mode and has an upper data bus and a lower data busand a control bus, the clock signal input of a first of said two visualdisplay units which is displaying one subarea being connected directlyto said control bus of the screen control unit, a counting gate circuit,the clock signal input of a second of said two visual display unitswhich is displaying an other subarea being connected via said countinggate circuit to the control bus of the screen control unit, and the datainputs of the two visual display units being connected in parallel tosaid upper and lower data buss of the screen control unit.
 5. A methodas claimed in claim 1, wherein said dual scan mode is a VGA dual scanmode of a VGA controller.